7721 Datasheet, PDF (360/577 Pages) List of Unclassifed Manufacturers – H Bridge Power Module

DMA CONTROLLER
13.8 Link array chain transfer mode
b23
b16 b15
b23
b16 b15
b8 b7
b8 b7
b0
Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0)
Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1)
Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2)
Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3)
Bit
Functions
23 to 0 ^[Write]
Set the start address of transfer parameter memory
of block which is first transferred.
These bits can be set to “00000016” to “FFFFFF16.”
[Read]
• After a value is written to this register and until
transfer starts, the read value indicates the written
value (the start address of the transfer parameter
memory of block which is first transferred).
• After transfer starts, the read value indicates the
source address of data which is next transferred.
Note: When writing to this register, write to all 24 bits.
At reset RW
Undefined RW
b0
Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0)
Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1)
Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2)
Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3)
Bit
Functions
At reset RW
23
to 0
Need not
[Read]
to be
set.
Undefined RW
After transfer starts, the read value indicates the
destination address of data which is next transferred.
b23
b16 b15
b8 b7
b0
Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3)
Bit
Functions
23 to 0 ^[Write]
Set the dummy data.
These bits can be set to “00000116” to “FFFFFF16.”
[Read]
• After a value is written to this register and until
transfer starts, the read value indicates the written
value (dummy data).
• After transfer starts, the read value indicates the
remaining byte number of the block which is being
transferred.
Note: When writing to this register, write to all 24 bits.
Do not write “00000016” to this register.
At reset RW
Undefined RW
Fig. 13.8.1 Register structures of SARi, DARi, and TCRi in link array chain transfer mode
7721 Group User‘s Manual
13-81