PD46184095B_15 Datasheet, PDF (7/34 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

μPD46184095B, μPD46184185B
Block Diagram
[μPD46184095B]
20
ADDRESS
LD#
ADDRESS
20
R, W#
REGISTRY
& LOGIC
K
K#
R, W#
BW0#
9
D0 to D8
LD#
K
K#
DATA
18
REGISTRY
& LOGIC
K
2²⁰ x 18
MEMORY
ARRAY
18
18
MUX
K
C, C#
OR
K, K#
[μPD46184185B]
19
ADDRESS
LD#
ADDRESS
19
R, W#
REGISTRY
& LOGIC
K
K#
R, W#
BW0#
BW1#
18
DATA
36
D0 to D17
REGISTRY
& LOGIC
LD#
K
K#
K
2¹⁹ x 36
MEMORY
ARRAY
36
36
MUX
K
C, C#
OR
K, K#
9
Q0 to Q8
2
CQ,
CQ#
18
Q0 to Q17
2
CQ,
CQ#
R10DS0115EJ0200 Rev.2.00
Nov 09, 2012
Page 7 of 34