PD46184095B_15 Datasheet, PDF (11/34 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

μPD46184095B, μPD46184185B
Bus Cycle State Diagram
LOAD NEW
ADDRESS
Count = 0
Load, Count = 2
Read
Load, Count = 2
Write
READ DOUBLE
Count = Count + 2
WRITE DOUBLE
Count = Count + 2
NOP,
Count = 2
NOP
NOP
Power UP
Supply voltage provided
Remark State machine control timing sequence is controlled by K.
NOP,
Count = 2
Load
R10DS0115EJ0200 Rev.2.00
Nov 09, 2012
Page 11 of 34