PD46184095B_15 Datasheet, PDF (10/34 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

μPD46184095B, μPD46184185B
Byte Write Operation
[μPD46184095B]
Operation
Write D0 to D8
Write nothing
K
L→H
−
L→H
−
K#
−
L→H
−
L→H
BW0#
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[μPD46184185B]
Operation
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
K
L→H
−
L→H
−
L→H
−
L→H
−
K#
−
L→H
−
L→H
−
L→H
−
L→H
BW0#
0
0
0
0
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0115EJ0200 Rev.2.00
Nov 09, 2012
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