PD46184095B_15 Datasheet, PDF (13/34 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

μPD46184095B, μPD46184185B
DC Characteristics 1 (TA = 0 to 70°C, V_DD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
Input leakage current
ILI
−2
I/O leakage current
ILO
−2
Operating supply current IDD VIN ≤ VIL or VIN ≥ VIH, -E33
(Read cycle / Write cycle)
II/O = 0 mA,
Cycle = MAX.
-E40
MAX.
x9 x18
+2
+2
500 530
Unit Note
μA
μA
mA
450 480
Standby supply current
(NOP)
Output HIGH voltage
Output LOW voltage
ISB1 VIN ≤ VIL or VIN ≥ VIH,
II/O = 0 mA,
Cycle = MAX.
Inputs static
VOH(Low) |IOH| ≤ 0.1 mA
VOH Note1
VOL(Low) IOL ≤ 0.1 mA
VOL Note2
-E33
390 400
-E40
380 380
V_DDQ−0.2
V_DDQ/2−0.12
V_SS
V_DDQ/2−0.12
V_DDQ
V_DDQ/2+0.12
0.2
V_DDQ/2+0.12
mA
V 3, 4
V 3, 4
V 3, 4
V 3, 4
Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0115EJ0200 Rev.2.00
Nov 09, 2012
Page 13 of 34