PD46184095B_15 Datasheet, PDF (19/34 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

μPD46184095B, μPD46184185B
Read and Write Timing
NOP
READ
(burst of 2)
READ
(burst of 2)
WRITE
(burst of 2)
WRITE
(burst of 2)
READ
(burst of 2)
NOP
1
2
3
4
5
6
7
8
K
TKHKL TKLKH
TKHKH
TKHK#H
K#
TK#HKH
LD#
R, W#
TIVKH
TKHIX
Address
Data in
A0
A1
TAVKH TKHAX
A2
A3
TDVKH TKHDX
A4
TDVKH TKHDX
D20
D21
D30
D31
Data out
CQ
CQ#
C
C#
Qx2
Q00
Q01 Q10 Q11
TCHQX1
TCHQX
TCHQV TCHQV
TCHQZ
TCHQX
TKHCH
TCHCQX
TCHCQV
TCHCQX
TCHCQV
TKHKL TKLKH
TKHKH
TKHK#H TK#HKH
TKHCH
TCQHQV
Q40
Q41
TCQHQX
TCQHCQ#H TCQ#HCQH
Remarks 1. Q01 refers to output from address A0+0.
Q02 refers to output from the next internal burst address following A0, i.e., A0+1.
2. Outputs are disabled (high impedance) 2.5 clock cycles after the last READ (LD# = LOW, R, W# =
HIGH) is input in the sequences of [READ]-[NOP] and [READ]-[WRITE].
3. In this example, if address A4 = A3, data Q41 = D31 and Q42 = D32.
Write data is forwarded immediately as read results.
R10DS0115EJ0200 Rev.2.00
Nov 09, 2012
Page 19 of 34