PD46184095B_15 Datasheet, PDF (17/34 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

μPD46184095B, μPD46184185B
Read and Write Cycle
Parameter
Symbol
Clock
Average Clock cycle time
(K, K#, C, C#)
Clock phase jitter (K, K#, C, C#)
Clock HIGH time (K, K#, C, C#)
Clock LOW time (K, K#, C, C#)
Clock HIGH to Clock# HIGH
(K → K#, C → C#)
Clock# HIGH to Clock HIGH
(K# → K, C# → C)
Clock to data clock
(K → C, K# → C#)
PLL lock time (K, C)
K static to PLL reset
TKHKH
TKC var
TKHKL
TKLKH
TKHK#H
TK#HKH
TKHCH
TKC lock
TKC reset
-E33,-E33Y
(300 MHz)
MIN.
MAX.
3.3
8.4
0.2
1.32
1.32
1.49
1.49
0
1.45
20
30
Output Times
CQ HIGH to CQ# HIGH
TCQHCQ#H 1.24
(CQ → CQ#)
CQ# HIGH to CQ HIGH
TCQ#HCQH 1.24
(CQ# → CQ)
C, C# HIGH to output valid
TCHQV
0.45
C, C# HIGH to output hold
TCHQX
−0.45
C, C# HIGH to echo clock valid TCHCQV
0.45
C, C# HIGH to echo clock hold TCHCQX
−0.45
CQ, CQ# HIGH to output valid TCQHQV
0.27
CQ, CQ# HIGH to output hold
TCQHQX
−0.27
C HIGH to output High-Z
TCHQZ
0.45
C HIGH to output Low-Z
TCHQX1
−0.45
Setup Times
Address valid to K rising edge
TAVKH
0.4
Synchronous load input (LD#),
TIVKH
0.4
read write input (R, W#) valid to
K rising edge
Data inputs and write data
TDVKH
0.3
select inputs (BWx#) valid to
K, K# rising edge
Hold Times
K rising edge to address hold
TKHAX
0.4
K rising edge to
TKHIX
0.4
synchronous load input (LD#),
read write input (R, W#) hold
K, K# rising edge to data inputs TKHDX
0.3
and write data select inputs
(BWx#) hold
-E40,-E40Y
(250 MHz)
MIN.
MAX.
4.0
8.4
0.2
1.6
1.6
1.8
1.8
0
1.8
20
30
1.55
1.55
0.45
−0.45
0.45
−0.45
0.3
−0.3
0.45
−0.45
0.5
0.5
0.35
0.5
0.5
0.35
Unit Note
ns
1
ns
2
ns
ns
ns
ns
ns
μs
3
ns
4
ns
5
ns
5
ns
ns
ns
ns
ns
6
ns
6
ns
ns
ns
7
ns
7
ns
7
ns
7
ns
7
ns
7
R10DS0115EJ0200 Rev.2.00
Nov 09, 2012
Page 17 of 34