PD46184095B_15 Datasheet, PDF (5/34 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

μPD46184095B, μPD46184185B
Pin Description
Symbol
A
Type
Input
D0 to Dxx Input
Q0 to Qxx Output
LD#
R, W#
BWx#
Input
Input
Input
K, K#
Input
C, C#
Input
(1/2)
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of K. All transactions operate on a burst of two words (one
clock period of bus activity). These inputs are ignored when device is deselected, i.e., NOP
(LD# = HIGH).
Synchronous Data Inputs: Input data must meet setup and hold times around the rising
edges of K and K# during WRITE operations. See Pin Arrangement for ball site location of
individual signals.
X9 device uses D0 to D8.
X18 device uses D0 to D17.
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K
and K# rising edges if C and C# are tied HIGH. Data is output in synchronization with C and
C# (or K and K#), depending on the LD# and R, W# command. See Pin Arrangement for
ball site location of individual signals.
X9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined.
This definition includes address and read/write direction. All transactions operate on a burst
of 2 data (one clock period of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type
(READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W#
must meet the setup and hold times around the rising edge of K.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold times
around the rising edges of K and K# for each of the two rising edges comprising the WRITE
cycle. See Pin Arrangement for signal to data relationships.
X9 device uses BW0#.
x18 device uses BW0#, BW1#.
See Byte Write Operation for relation between BWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of
K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180
degrees out of phase with K. All synchronous inputs must meet setup and hold times around
the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data.
The rising edge of C# is used as the output timing reference for first output data. The rising
edge of C is used as the output reference for second output data. Ideally, #C is 180 degrees
out of phase with C. When use of K and K# as the reference instead of C and C#, then fixed
C and C# to HIGH. Operation cannot be guaranteed unless C and C# are fixed to HIGH
(i.e. toggle of C and C#)
R10DS0115EJ0200 Rev.2.00
Nov 09, 2012
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