PD46184095B_15 Datasheet, PDF (28/34 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

μPD46184095B, μPD46184185B
Boundary Scan Register Status of Output Pins CQ, CQ# and Q
Instructions
EXTEST
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
SRAM Status
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
Boundary Scan Register Status
CQ,CQ#
Q
Pad
Pad
Pad
Pad
−
−
−
−
Pad
Pad
Pad
Pad
Internal
Internal
Internal
Pad
−
−
−
−
Note
No definition
No definition
Remark The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mode.
There are two statuses:
Boundary Scan
Register
CAPTURE
Register
Pad : Contents of the output pin (DDR Pad) are captured
Pad
in the “CAPTURE Register” in the Boundary Scan
Update
Register
Register.
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
DDR
Pad
SRAM
Output
Driver
Internal
SRAM
Output
High-Z
JTAG ctrl
R10DS0115EJ0200 Rev.2.00
Nov 09, 2012
Page 28 of 34