H8S2214 Datasheet, PDF (682/936 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 17 Power-Down Modes
17.2.2 System Clock Control Register (SCKCR)
Bit
:7
6
5
PSTOP —
—
Initial value : 0
0
0
R/W
: R/W
R/W
—
4
3
2
1
0
—
—
SCK2 SCK1 SCK0
0
0
0
0
0
—
R/W R/W R/W R/W
SCKCR is an 8-bit readable/writable register that performs φ clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Bit 7
PSTOP
0
1
Description
High–Speed Mode
Medium-Speed Mode Sleep Mode
φ output (initial value) φ output
Fixed high
Fixed high
Software Standby Hardware
Mode, Watch
Standby Mode
Fixed high
Fixed high
High impedance
High impedance
Bits 6 and 3—Reserved: These bits can be read or written to, but should only be written with 0.
Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus
master in high-speed mode and medium-speed mode.
Bit 2
SCK2
0
1
Bit 1
SCK1
0
1
0
1
Bit 0
SCK0
0
1
0
1
0
1
—
Description
Bus master is in high-speed mode
Medium-speed clock is φ/2
Medium-speed clock is φ/4
Medium-speed clock is φ/8
Medium-speed clock is φ/16
Medium-speed clock is φ/32
—
(Initial value)
Rev.4.00 Sep. 18, 2008 Page 622 of 872
REJ09B0189-0400