H8S2214 Datasheet, PDF (155/936 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 5 Interrupt Controller
5.2.2
Interrupt Priority Registers A to D, F, G, J, K, M (IPRA to IPRD, IPRF, IPRG,
IPRJ, IPRK, IPRM)
Bit
:
7
6
5
4
3
2
1
0
—
IPR6 IPR5 IPR4
—
IPR2 IPR1 IPR0
Initial value:
0
1
1
1
0
1
1
1
R/W
:
—
R/W R/W R/W
—
R/W
R/W
R/W
The IPR registers are nine 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5.3.
The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
They are not initialized in software standby mode.
Bits 7 and 3—Reserved: Read-only bits, always read as 0.
Table 5.3 Correspondence between Interrupt Sources and IPR Settings
Bits
Register
6 to 4
2 to 0
IPRA
IRQ0
IRQ1
IPRB
IRQ2
IRQ3
IRQ4
IRQ5
IPRC
IPRD
IRQ6
IRQ7
Watchdog timer 0
DTC
—^*
IPRF
TPU channel 0
TPU channel 1
IPRG
TPU channel 2
—
IPRJ
DMAC
SCI channel 0
IPRK
SCI channel 1
SCI channel 2
IPRM
EXIRQ3 to EXIRQ0
EXIRQ7 to EXIRQ4
Note: * Reserved bits. These bits cannot be modified and are always read as 1.
Rev.4.00 Sep. 18, 2008 Page 95 of 872
REJ09B0189-0400