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| H8S2214 Datasheet, PDF (25/936 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series | |||
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Item
A.5 Bus States
during Instruction
Execution
Table A.16
Instruction
Execution Cycles
Page
724
729
730
A.6 Condition
733
Code Modification
Table A.17
Condition Code
Modification
735
736
B.2 Functions
785
TCR1âTimer
Control Register 1
Revisions (See Manual for Details)
Note added
Instruction
1
2
3
4
5
6
7
8
9
LDM.L @SP+,
R:W 2nd
R:W:M NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3
(ERnâERn+1)*9
1 state
LDM.L @SP+,(ERnâERn+2)*9 R:W 2nd
R:W NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3
1 state
LDM.L @SP+,(ERnâERn+3)*9 R:W 2nd
R:W NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3
1 state
Note added
Instruction
1
2
3
4
5
6
7
8
9
STM.L(ERnâERn+1),@âSP*9 R:W 2nd
R:W:M NEXT Internal operation, W:W:M stack (H)*3 W:W stack (L)*3
1 state
STM.L(ERnâERn+2),@âSP*9 R:W 2nd
R:W:M NEXT Internal operation, W:W:M stack (H)*3 W:W stack (L)*3
1 state
STM.L(ERnâERn+3),@âSP*9 R:W 2nd
R:W:M NEXT Internal operation, W:W:M stack (H)*3 W:W stack (L)*3
1 state
Note added
Notes : 9. The STM/LDM instructions may only be used with the
ER0 to ER6 registers.
Note added
Instruction
LDM*2
HNZ VC
âââââ
Definition
Note added
Instruction
STM*2
HNZ VC
âââââ
Definition
Note added
Instruction
TAS*1
HNZ VC
â
0â
Definition
N = Dm
Z = Dm · Dmâ1 · ...... · D0
Notes : 2. The STM/LDM instructions may only be used with the
ER0 to ER6 registers.
Description added
Clock Edge 1 and 0
0 0 Count at rising edge
1 Count at falling edge
1 â Count at both edges
Note: The internal clock edge selection is valid when the input
clock is Ï/4 or slower. This setting is ignored if the input
clock is Ï/1, or when overflow/underflow of another
channel is selected. (Counting occurs on the falling edge
of Ï when Ï/1 is selected.)
Rev.4.00 Sep. 18, 2008 Page xxv of lx
REJ09B0189-0400
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