H8S2214 Datasheet, PDF (46/936 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Figure 4.7
Reset Sequence (Mode 4).......................................................................................... 85
Interrupt Sources and Number of Interrupts.............................................................. 87
Stack Status after Exception Handling
(Normal Modes: Not available in the H8S/2214)...................................................... 89
Stack Status after Exception Handling (Advanced Modes) ...................................... 89
Operation when SP Value Is Odd.............................................................................. 90
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller...................................................................... 92
Figure 5.2 Block Diagram of Interrupts IRQn.......................................................................... 100
Figure 5.3 Timing of Setting IRQnF ........................................................................................ 100
Figure 5.4 Block Diagram of Interrupt Control Operation ....................................................... 105
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0.. 108
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2.. 110
Figure 5.7 Interrupt Exception Handling.................................................................................. 111
Figure 5.8 Contention between Interrupt Generation and Disabling ........................................ 114
Figure 5.9 Interrupt Control for DTC and DMAC ................................................................... 116
Section 6 Bus Controller
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Block Diagram of Bus Controller ........................................................................... 120
Overview of Area Divisions.................................................................................... 134
CSn Signal Output Timing (n = 0 to 7) ................................................................... 138
Access Sizes and Data Alignment Control (8-Bit Access Space) ........................... 139
Access Sizes and Data Alignment Control (16-Bit Access Space) ......................... 140
Bus Timing for 8-Bit 2-State Access Space ............................................................ 142
Bus Timing for 8-Bit 3-State Access Space ............................................................ 143
Bus Timing for 16-Bit 2-State Access Space (Even Address Byte Access)............ 144
Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (Odd Address Byte Access) ............. 145
Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (Word Access) ................................. 146
Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (Even Address Byte Access)............ 147
Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (Odd Address Byte Access) ............. 148
Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (Word Access) ................................. 149
Figure 6.14 Example of Wait State Insertion Timing................................................................. 151
Figure 6.15 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1).................. 153
Figure 6.16 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0).................. 154
Figure 6.17 Example of Idle Cycle Operation (1) ...................................................................... 155
Figure 6.18 Example of Idle Cycle Operation (2) ...................................................................... 156
Figure 6.19 Relationship between Chip Select (CS) and Read (RD) ......................................... 157
Figure 6.20 Bus-Released State Transition Timing.................................................................... 161
Figure 6.21 Multichip Block Diagram........................................................................................ 165
Figure 6.22 Timing of External Module Area Access by DTC .................................................. 171
Rev.4.00 Sep. 18, 2008 Page xlvi of lx
REJ09B0189-0400