H8S2214 Datasheet, PDF (582/936 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 12 Serial Communication Interface (SCI)
(6) Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission.
Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
(7) Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer
rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the
basic clock. This is illustrated in figure 12.26.
16 clocks
8 clocks
0
7
Internal basic
clock
15 0
7
15 0
Receive data
(RxD)
Synchronization
sampling timing
Start bit
D0
D1
Data sampling
timing
Figure 12.26 Receive Data Sampling Timing in Asynchronous Mode
Rev.4.00 Sep. 18, 2008 Page 522 of 872
REJ09B0189-0400