M16C30P Datasheet, PDF (46/57 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.43 Memory Expansion and Microprocessor Modes (for setting with no wait)
Symbol
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
ALE Signal Output Hold Time
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) ⁽³⁾
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR) ⁽³⁾
HLDA Output Delay Time
Standard
Unit
Min.
Max.
30
ns
0
ns
0
ns
(NOTE 2)
ns
30
ns
0
ns
25
ns
−4
ns
See
Figure 5.8
30
ns
0
ns
30
ns
0
ns
40
ns
4
ns
(NOTE 1)
ns
(NOTE 2)
ns
40
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
-0----.-5----x----1---0---9---
f(BCLK)
–
40
[
n
s]
f(BCLK) is 12.5MHz or less.
2. Calculated according to the BCLK frequency as follows:
f-0--(^{--.B-5----Cx----1L---0-K--9---}) ^{– 10[ns]}
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC1)
by a circuit of the right figure.
For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1k Ω X In(1−0.2VCC1 / VCC1)
= 6.7ns.
R
DBi
C
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
Figure 5.8 Ports P0 to P10 Measurement Circuit
30pF
Rev.1.22 Mar 30, 2007 Page 46 of 53
REJ03B0088-0122