M16C30P Datasheet, PDF (17/57 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/30P Group
3. Memory
3. Memory
Figure 3.1 is a Memory Map of the M16C/30P group. The address space extends the 1 Mbyte from address 00000h to
FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte
internal ROM is allocated to the addresses from F0000h to FFFFFh.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start
address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 5-Kbyte
internal RAM is allocated to the addresses from 00400h to 017FFh. In addition to storing data, the internal RAM also
stores the stack used when calling subroutines and when interrupts are generated. The SFR is allocated to the addresses
from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no
functions allocated is reserved for future use and cannot be used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS
or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
00000h
SFR
00400h
Internal RAM
XXXXXh
0F000h
0FFFFh
10000h
Reserved area ⁽¹⁾
Internal ROM
(data area) ^{(3, 4)}
External area
FFE00h
Special page
vector table
27000h
Internal RAM
Size Address XXXXXh
5 Kbytes
017FFh
6 Kbytes
12 Kbytes
01BFFh
033FFh
Internal ROM ⁽⁵⁾
Size Address YYYYYh
96 Kbytes
E8000h
128 Kbytes
160 Kbytes
E0000h
D8000h
192 Kbytes
256 Kbytes
D0000h
C0000h⁽⁶⁾
28000h
D0000h
YYYYYh
FFFFFh
Reserved area
External area
Reserved area ^{(2, 4)}
Internal ROM
(program area) ⁽⁵⁾
FFFDCh
FFFFFh
NOTES:
1. During memory expansion and microprocessor modes, can be used.
2. In memory expansion mode, can be used.
3. As for the flash memory version, 4-Kbyte space (block A) exists.
4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1” .
5. When using the masked ROM version, write nothing to internal ROM area.
6. When the PM13 bit is set to "0", the address of Internal ROM becomes D0000h, and when
the PM13 bit is set to "1", the address becomes C0000h.
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
Figure 3.1 Memory Map
Rev.1.22 Mar 30, 2007 Page 17 of 53
REJ03B0088-0122