7641_06 Datasheet, PDF (328/385 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7641 Group
APPENDIX
3.5 Control registers
3.5 Control registers
CPU mode register A
b7 b6 b5 b4 b3 b2 b1 b0
1
CPU mode register A
(CPMA : address 0016)
b
Name
Functions
At reset R W
0 ^{Processor mode bits}
b1b0
0
0 0 : Single-chip mode
1
0 1 : Memory expansion mode
1 0 : Microprocessor mode (Note 1)
0
1 1 : Not available
2 Stack page select bit
0 : Page 0
1
1 : Page 1
3 Fix this bit to “1”.
1
4 ^{Sub-clock (XCIN-XCOUT)} 0 : Stopped
0
stop bit
1 : Oscillating
5 ^{Main clock (XIN-XOUT) stop 0 : Oscillating}
0
bit
1 : Stopped
6 ^{Internal system clock}
select bit (Note 2)
0 : External clock (XIN-XOUT or XCIN-XCOUT) 0
1 : fsyn
7 External clock select bit 0 : XIN-XOUT
0
1 : XCIN-XCOUT
Notes 1: This is not available in the flash memory version.
2: When (CPMA 7, 6) = (0, 0), the internal system clock can be selected between
f(XIN) and f(XIN)/2 by CCR7.
The internal clock φ is the internal system clock divided by 2.
Fig. 3.5.1 Structure of CPU mode register A
CPU mode register B
b7 b6 b5 b4 b3 b2 b1 b0
10
CPU mode register B
(CPMB : address 0116)
b
Name
0 Slow memory wait select
bits
1
2 Slow memory wait mode
select bits
3
4 Expanded data memory
access bit
5 ^{HOLD function enable bit}
6 Fix this bit to “0”.
7 Fix this bit to “1”.
Functions
b1b0
0 0 : No wait
0 1 : One-time wait
1 0 : Two-time wait
1 1 : Three-time wait
b3b2
0 0 : Software wait
0 1 : Not available
1 0 : RDY wait
1 1 : Software wait plus RDY input
anytime wait anytime wait
0 : EDMA output disabled
1 : EDMA output enabled
0 : HOLD function disabled
1 : HOLD function enabled
Fig. 3.5.2 Structure of CPU mode register B
Rev.2.00 Aug 28, 2006 page 49 of 108
REJ09B0336-0200
At reset R W
1
1
0
0
0
0
0
1