7641_06 Datasheet, PDF (256/385 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7641 Group
APPLICATION
2.10 External devices connection
(3) Software wait + Extended RDY wait
Extended RDY wait (software wait plus RDY input anytime wait) is selected by setting “11” to the
slow memory wait mode select bits (b3, b2 of CPMB). The read/write cycle can be extended when
a fixed time (tsu) of “L” is input to the RDY pin at the beginning of a read/write cycle (before φ cycle
falls). The RDY pin state is checked continually at each fall of φ cycle until the RDY pin goes to “H”
and the cycle keeps being extended. When a fixed time of “H” (tsu) is input to the RDY pin at the
beginning of a read/write cycle (before φ cycle falls), the MCU is released from the wait within 1, 2,
or 3 φ cycles as selected with the slow memory wait bits (b1, b0 of CPMB).
Figure 2.10.6 shows the extended RDY wait (software wait plus RDY input anytime wait) timing
example
<< No Wait >>
1 bus cycle
φOUT
ADOUT
DB IN/OUT
RD
WR
Address
IN
Address
OUT
<< Wait >>
1 bus cycle
φOUT
ADOUT
DB IN/OUT
RD
WR
RDY
Address
IN
tsu
tsu ^tsu
tsu
1
2
3
4
1. When a fixed time (tsu) of “L” is input to the RDY pin before φ falls, the MCU goes to RDY state.
2. The RDY pin state is checked continually at each fall of φ cycle.
3. The RDY pin is “L” at the φ fall of the end of the current wait time, so that the read/write cycle is
extended for one wait once again.
4. When a fixed time (tsu) of “H” is input to the RDY pin before φ falls, the RDY state is released after
the current wait time.
Note: This example is the 1-cycle extended RDY wait (RD).
The 1-cycle extended RDY wait (WR) is the same timing as this.
Refer to Chapter 1 “Slow Memory Wait in PROCESSOR MODE” for 2- and 3-cycle
extended RDY wait timings.
Fig. 2.10.6 Extended RDY wait (software wait plus RDY input anytime wait) timing example
Rev.2.00 Aug 28, 2006 page 125 of 148
REJ09B0336-0200