7641_06 Datasheet, PDF (244/385 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7641 Group
APPLICATION
2.8 Master CPU bus interface
2.8.4 Operation description
(1) Input operation
The bus interface input operation is explained as the following:
➀ When the logical OR of Sx (x = 0, 1) and W is “0”, the data bus state is latched into the input data
bus buffer register x (x = 0, 1) at the rising of W input signal.
➁ When the data is latched into the input data bus buffer register x, the Input Buffer Full Flag (IBFx
; x = 0, 1) of the data bus buffer status register x (x = 0, 1) is simultaneously set to “1”.
➂ When the IBFx flag is set to “1”, the input buffer full interrupt request occurs.
➃ At the timing ➂, the A0 level is stored into the A0 flag, bit 3 of the data bus buffer status register
x. Refer to the A0 flag to judge whether the read contents of the input data bus buffer register x
are data or a command.
(2) Output operation
The bus interface output operation is explained as the following:
➀ Writing data to the output data bus buffer register x (x = 0, 1) sets the Output Buffer Full Flag
(OBFx ; x = 0, 1) of the data bus buffer status register x to “1”.
➁ When the logical OR of Sx, R and A0 is “0”, the contents of the output data bus buffer register
x are output on the data bus and the OBFx flag is simultaneously cleared to “0”.
➂ At the rising of the R input signal, the output buffer empty interrupt request occurs.
Rev.2.00 Aug 28, 2006 page 113 of 148
REJ09B0336-0200