7641_06 Datasheet, PDF (293/385 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7641 Group
APPENDIX
3.1 Electrical characteristics
In Vcc = 3 V
Table 3.1.13 Master CPU bus interface (MBI; RD, WR separate type) (Vcc = 3.0 to 3.6 V, Vss = 0 V,
Ta = –20 to 70°C, unless otherwise noted)
Symbol
tsu(S-R)
tsu(S-W)
th(R-S)
th(W-S)
tsu(A-R)
tsu(A-W)
th(R-A)
th(W-A)
tw(R)
tw(W)
tsu(D-W)
th(W-D)
ta(R-D)
tv(R-D)
tv(R-OBF)
td(W-IBF)
Parameter
S0, S1 setup time for read
S0, S1 setup time for write
S0, S1 hold time for read
S0, S1 hold time for write
A0 setup time for read
A0 setup time for write
A0 hold time for read
A0 hold time for write
Read pulse width
Write pulse width
Data input setup time before write
Data input hold time after write
Data output enable time after read
Data output disable time after read
OBF output transmission time after read
IBF output transmission time after write
Limits
Unit
Min.
Typ.
Max.
0
ns
0
ns
0
ns
0
ns
10
ns
10
ns
0
ns
0
ns
80
ns
80
ns
35
ns
0
ns
65
ns
10
ns
50
ns
50
ns
In Vcc = 3 V
Table 3.1.14 Master CPU bus interface (MBI; R/W type) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to
70°C, unless otherwise noted)
Symbol
tsu(S-E)
th(E-S)
tsu(A-E)
th(E-A)
tsu(RW-E)
th(E-RW)
tw(E)
tw(E-E)
tsu(D-E)
th(E-D)
ta(E-D)
tv(E-D)
tv(E-OBF)
td(E-IBF)
Parameter
S0, S1 setup time
S0, S1 hold time
A0 setup time
A0 hold time
R/W setup time
R/W hold time
Enable pulse width
Enable pulse interval
Data input setup time before write
Data input hold time after write
Data output enable time after read
Data output disable time after read
OBF output transmission time after E inactive
IBF output transmission time after E inactive
Limits
Unit
Min.
Typ.
Max.
0
ns
0
ns
10
ns
0
ns
10
ns
10
ns
80
ns
80
ns
35
ns
0
ns
65
ns
10
ns
50
ns
50
ns
Rev.2.00 Aug 28, 2006 page 14 of 108
REJ09B0336-0200