7641_06 Datasheet, PDF (263/385 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7641 Group
APPLICATION
2.10 External devices connection
2.10.8 Notes on external devices connection
(1) Rewrite port P3 latch
In both memory expansion mode and microprocessor mode, ports P31 and P32 can be used as output
ports. We recommend to use the LDM instruction or STA instruction to write to port P3 register
(address 000E16). If using the Read-Modify-Write instruction (SEB instruction, CLB instruction) you
will need to map a memory that the CPU can read from and write to.
[Reason]
The access to address 000E16 is performed:
•Read from external memory
•Write to both port P3 latch and external memory.
It is because address 000E16 is assigned on an external area In the memory expansion mode and
microprocessor mode.
Accordingly, if a Read-Modify-Write instruction is executed to address 000E16, the external memory
contents is read out and after its modification it will be written into both port P3 latch and an external
memory. As a result, if an external memory is not allocated in address 000E16 then, the MCU will read
an undefined value and write its modified value into the port P3 latch. Therefore port P3 latch value
will become undefined.
(2) overlap of internal and external memories
In the memory expansion mode, if the internal and external memory areas overlap, the internal
memory becomes the valid memory for the overlapping area. When the CPU performs a read or a
write operation on this overlapped area, the following things happen:
•Read
The CPU reads out the data in the internal memory instead of in the external memory. Note that,
since the CPU will output a proper read signal, address signal, etc., the memory data at the
respective address will appear on the external data bus.
•Write
The CPU writes data to both the internal and external memories.
_____ ______
(3) RD, WR pins
In the memory expansion mode or microprocessor mode, a read-out control signal is output from the
______
______
RD pin (P36), and a write-in control signal is output from the WR pin (P37). “L” level is output from
______
______
the RD pin at CPU read-out and from the WR pin at CPU write-in. These signals function for internal
access and external access.
__________
(4) HLDA pin
__________
In spite of enabling the Hold function, the HLDA pin does not function when IBF1 output is enabled
in the master CPU bus interface.
Rev.2.00 Aug 28, 2006 page 132 of 148
REJ09B0336-0200