7641_06 Datasheet, PDF (268/385 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7641 Group
APPLICATION
2.12 Clock generating circuit
Frequency synthesizer control register
b7 b6 b5 b4 b3 b2 b1 b0
0 00
Frequency synthesizer control register
(FSC : address 6C16)
b
Name
Functions
At reset R W
0 ^{Frequency synthesizer}
0 : Disabled
0
enable bit (FSE)
1 : Enabled
1 Fix these bits to “0”.
0
2
0
3 ^{Frequency synthesizer}
0 : f(XIN)
0
input bit (FIN)
1 : f(XCIN)
4 Fix this bit to “0”.
0
5 ^{LPF current control bit}
b1b0
1
(CHG1, CHG0) (Note)
0 0 : Not available
0 1 : Low current
6
1 0 : Intermediate current (recommended) 1
1 1 : High current
7 Frequency synthesizer 0 : Unlocked
0
lock status bit
1 : Locked
Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset.
When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after
locking the frequency synthesizer.
Fig. 2.12.4 Structure of Frequency synthesizer control register
Frequency synthesizer multiply register 1
b7 b6 b5 b4 b3 b2 b1 b0
Frequency synthesizer multiply register 1
(FSM1: address 6D16)
b
Functions
At reset R W
0 qfVCO clock is generated by multiplying fPIN clock, which is generated 1
1 ^{by FSM2, by the contents of this register:}
1
2
1
3 ^{fVCO = fPIN • {2(n +1)}, n: value set to FSM1.}
1
4
1
5
1
6
1
7
1
Fig. 2.12.5 Structure of Frequency synthesizer multiply register 1
Rev.2.00 Aug 28, 2006 page 137 of 148
REJ09B0336-0200