7641_06 Datasheet, PDF(222/385 Page) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

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7641_06 Datasheet, PDF (222/385 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

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7641 Group

APPLICATION

2.5 DMAC

Table 2.5.2 Address directions and examples of transfer result (2)

Address direction

Data arrangement on

Transfer

Source

Destination transfer source memory

sequence

Forward

Backward

*

Data 1

â

Data 2

â

â

Data 3

â

Data 4 â

Data 5 â

Data 6

Data arrangement on

transfer destination memory

(Ttransfer result)

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1 *

Backward

Fixed

Backward

Forward

Backward

Backward

â

Data 6

â

Data 5

â

Data 4

â

Data 3 â

Data 2

â

* Data 1

Data 6 â

Data 5

â

Data 4

â

â

Data 3

â

Data 2

â

* Data 1

â

D at a 16

â

D at a 25

â

D at a 34

â

Data 43

â

D at a 52

â

* Data 61

Data 1 to 6 *

Data 1 *

Data 2

Data 3

Data 4

Data 5

Data 6

D at a 16

D at a 25

D at a 34

Data 43

D at a 52

Data 61 *

(4) Transfer suspension

Writing â0â to the DMAC channel x enable bit (DxCEN) can compulsorily suspend the transfer being

executed. The suspended transfer can be resumed by writing â1â to the DxCEN bit.

When an interrupt request, which is enabled, occurs during any DMA operation, the transfer operation

is suspended and the interrupt process routine is initiated. During the interrupt operation, the DMAC

automatically sets the corresponding DMAC channel x suspend flag to â1â. When the DMAC transfer

suspend control bit (DTSC) is â1â, the transfer is suspended in both burst transfer and cycle steal

transfer modes during an interrupt process; when the DTSC bit is â0â, it is suspended in only burst

transfer mode.

The suspended transfer due to the interrupt can also be resumed during its interrupt process routine

by writing â1â to the DxCEN bit.

Rev.2.00 Aug 28, 2006 page 91 of 148

REJ09B0336-0200

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