7641_06 Datasheet, PDF (269/385 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7641 Group
APPLICATION
2.12 Clock generating circuit
Frequency synthesizer multiply register 2
b7 b6 b5 b4 b3 b2 b1 b0
Frequency synthesizer multiply register 2
(FSM2: address 6E16)
b
Functions
At reset R W
0 qfPIN clock is generated by dividing fIN clock by the contents of this 1
1 ^register.
1
2 ^{Either f(XIN) or f(XCIN) as an input clock fIN for the frequency} 1
3 ^{synthesizer is selectable.}
1
4 _{fPIN = fIN / {2(n +1)}, n: value set to FSM2}
1
5
1
6
1
7
1
Fig. 2.12.6 Structure of Frequency synthesizer multiply register 2
Frequency synthesizer divide register
b7 b6 b5 b4 b3 b2 b1 b0
Frequency synthesizer divide register
(FSD: address 6F16)
b
Functions
At reset R W
0 qfSYN clock is generated by dividing fVCO clock by the contents of this 1
1 ^register:
1
2
1
3 ^{fSYN = fVCO / {2(m +1)}, m: value set to FSD}
1
4
1
5
1
6
1
7
1
Fig. 2.12.7 Structure of Frequency synthesizer divide register
Rev.2.00 Aug 28, 2006 page 138 of 148
REJ09B0336-0200