R0E00008AKCE00EP62 Datasheet, PDF (27/82 Pages) Renesas Technology Corp – Microcomputer Development Environment System

Section 5 Differences between the MCUs and the Emulator
19. Initializing the Internal I/O Register with the Reset_CPU Function
Be sure to initialize the internal I/O registers shown below by the user program since they are
not initialized by selecting [Debug] – [Reset CPU] or using the RESET command.
Table 5.3 Registers Not Initialized
MCU Name
H8/3664F
H8/3687F
H8/3694F
H8/36037F
H8/36057F
H8/36049F
H8/36064F
H8/36087F
H8/36109F
H8/36077F
H8/36079F
H8/36094F
Register Not Initialized
IEGR1, IEGR2, IENR1, IRR1, IWPR, MSTCR1, TSCR
IEGR1, IEGR2, IENR1, IENR2, IRR1, IRR2, IWPR, MSTCR1, MSTCR2
IEGR1, IEGR2, IENR1, IRR1, IWPR, MSTCR1
IEGR1, IEGR2, IENR1, IENR2, IRR1, IRR2, IWPR, MSTCR1, MSTCR2
IEGR1, IEGR2, IENR1, IENR2, IRR1, IRR2, IWPR, MSTCR1, MSTCR2
IEGR1, IEGR2, IENR1, IENR2, IRR1, IRR2, IWPR, MSTCR1, MSTCR2
IEGR1, IEGR2, IENR1, IENR2, IRR1, IRR2, IWPR, MSTCR1, MSTCR2
IEGR1, IEGR2, IENR1, IENR2, IRR1, IRR2, IWPR, MSTCR1, MSTCR2
IEGR1, IEGR2, IENR1, IENR2, IRR1, IRR2, IWPR, MSTCR1, MSTCR2
IEGR1, IEGR2, IENR1, IRR1, IWPR, MSTCR1
20. Step Execution of the SLEEP Instruction
When the interrupt mask bit (I) in the condition code register (CCR) is 1, do not perform step
execution of the SLEEP instruction. If the step execution is performed and not finished
correctly, restart the emulator.
21. Processing at Emulator Activation (H8/36064(G)F, H8/36077(G)F, H8/36094(G)F, and
H8/36109(G)F)
When the emulator is activated, the watchdog timer is not active; the operation of the emulator
differs from that of the MCU.
Rev. 1.00 Aug.03, 2009 Page 21 of 26
REJ10J2022-0100