M306V5ME-XXXSP Datasheet, PDF (119/263 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
M306V5EESP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.11.6 Multi-master I²C-BUS Interface 0 and Multi-master I²C-BUS Interface 1
The multi-master I²C-BUS interface 0 and 1 have each dedicated circuit and operate independently.
The multi-master I²C-BUS interface i is a serial communications circuit, conforming to the Philips I²C-
BUS data transfer format. This interface i, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figures 2.11.32 and Figure 2.11.33 show a block diagram of the multi-master I²C-BUS interface i and
Table 2.11.13 shows multi-master I²C-BUS interface i functions.
This multi-master I²C-BUS interface i consists of the I²Ci address register, the I²Ci data shift register, the
I²Ci clock control register, the I²Ci control register, the I²Ci status register, the I²Ci port selection register
and other control circuits.
Table 2.11.13 Multi-master I²C-BUS Interface Functions
Item
Format
Communication mode
SCL clock frequencyn
Function
In conformity with Philips I²C-BUS standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I²C-BUS standard:
Master transmission Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at BCLK = 10 MHz)
Note : We are not responsible for any third party’s infringement of patent rights or other rights attributable
to the use of the control function (bits 6 and 7 of the I²C control register at address 027D16) for
connections between the I²C-BUS interface 0 and ports (SCL1, SCL2, SDA1, SDA2).
Rev. 1.0
118