PM7375 Datasheet, PDF (404/430 Pages) PMC-Sierra, Inc – ATM SAR and PHY Processor for PCI Bus

DATA SHEET
PMC-931127
ISSUE 6
PM7375 LASAR-155
LOCAL ATM SAR & PHYSICAL LAYER
5. In non-multiplexed address/data bus architecture's, ALE should be held high,
parameters tS_ALR, tH_ALR, tV_L, and tS_LR are not applicable.
6. Parameter tH_AR is not applicable if address latching is used.
7. When a set-up time is specified between an input and a clock, the set-up time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point
of the clock.
8. When a hold time is specified between an input and a clock, the hold time is the
time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of
the clock.
Microprocessor Interface Slave Write Access (Fig. 17.2)
Symbol
tS_AW
tS_DW
tS_ALW
tH_ALW
tV_L
tS_LW
tH_LW
tH_DW
tH_AW
tV_WR
Parameter
Address to Valid Write Set-up Time
Data to Valid Write Set-up Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
Latch to Write Set-up
Latch to Write Hold
Data to Valid Write Hold Time
Address to Valid Write Hold Time
Valid Write Pulse Width
Min Typ Max Units
10
ns
20
ns
10
ns
10
ns
20
ns
0
ns
5
ns
5
ns
5
ns
40
ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 388