PM7375 Datasheet, PDF (356/430 Pages) PMC-Sierra, Inc – ATM SAR and PHY Processor for PCI Bus

DATA SHEET
PMC-931127
ISSUE 6
PM7375 LASAR-155
LOCAL ATM SAR & PHYSICAL LAYER
13.2 Power Sequencing
Due to ESD protection structures in the pads it is necessary to exercise caution
when powering a device up or down. ESD protection devices behave as diodes
between power supply pins and from I/O pins to power supply pins. Under extreme
conditions it is possible to damage these ESD protection devices or trigger latch up.
The recommended power supply sequencing is as follows:
1.) VDD_DC power must be supplied either before VDD_AC or simultaneously
with VDD_AC to prevent current flow through the ESD protection devices
which exist between VDD_DC and VDD_AC power supplies. Connection to
a common VDD power plane is the recommended standard practice for
customer applications.
2.) To prevent damage to the ESD protection on the device inputs the
maximum DC input current specification must be respected. This is
accomplished by either ensuring that the VDD_DC power is applied before
input pins are driven or by increasing the source impedance of the driver so
that the maximum driver short circuit current is less than the maximum DC
input current specification (20 mA).
3.) Analog power supplies must be applied after both VDD_DC and VDD_AC
have been applied or the they must be current limited to the maximum
latchup current specification (100 mA). To prevent forward biasing the ESD
protection diode between AVD supplies and VDD_DC, the differential
voltage measured between these power supplies must be less than 0.5 volt.
This recommended differential voltage is to include peak to peak noise on
the VDD_DC power supply as digital noise will otherwise be coupled into
the analog circuitry. Current limiting can be accomplished by using an off
chip three terminal voltage regulator supplied by a quiet high voltage
supply. If the VDD power supply is relatively quiet, VDD can be filtered
using a ferrite bead and a high frequency decoupling capacitor to supply
AVD. The relative power sequencing of the multiple AVD power supplies is
not important.
4.) Power down the device in the reverse sequence. Use the above current
limiting technique for the analog power supplies. Small offsets in VDD and
AVD discharge times will not damage the device.
13.3 Interfacing to ECL or PECL Devices
Although the TXD+/- outputs are TTL compatible, only a few passive components
are required to convert the signals to ECL (or PECL) logic levels. The figure below
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 340