PM7375 Datasheet, PDF (281/430 Pages) PMC-Sierra, Inc – ATM SAR and PHY Processor for PCI Bus

DATA SHEET
PMC-931127
ISSUE 6
PM7375 LASAR-155
LOCAL ATM SAR & PHYSICAL LAYER
10.4.8 Register 0x31C: PCID Rx Queue Base
Bit
Bit 31
to
Bit 0
Type
R/W
Function
Default
RQB[31:0] XXXXXXXXH
RQB[31:0]:
The RQB[31:0] bits define the base address of the Receive Packet Descriptor
Reference Large Buffer Free, Receive Packet Descriptor Reference Small Buffer
Free, Receive Packet Descriptor Reference Ready, Receive Management
Descriptor Reference Free and Receive Management Descriptor Reference
Ready queues. This register is initialized by the PCI Host. To calculate the
physical address of a particular receive queue element, the RQB bits are added
to the appropriate queue start, end, read or write index registers to form the
physical address.
The base address must be DWORD aligned and thus the least significant
2 bits must be written to logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 265