PM7375 Datasheet, PDF (156/430 Pages) PMC-Sierra, Inc – ATM SAR and PHY Processor for PCI Bus

DATA SHEET
PMC-931127
ISSUE 6
PM7375 LASAR-155
LOCAL ATM SAR & PHYSICAL LAYER
10.1.34
Register 0x39 (0x0E4): RPOP Path BIP-8 MSB
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
PBE[15]
PBE[14]
PBE[13]
PBE[12]
PBE[11]
PBE[10]
PBE[9]
PBE[8]
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
These registers allow path BIP-8 errors to be accumulated.
PBE[15:0]:
Bits PBE[15:0] represent the number of path BIP-8 errors (B3) that have been
detected since the last time the error count was polled. The error count is polled
by writing to either of the RPOP Path BIP-8 Register addresses or to either of the
RPOP Path FEBE Register addresses. Such a write transfers the internally
accumulated error count to the Path BIP-8 Registers within approximately 7 µs
and simultaneously resets the internal counter to begin a new cycle of error
accumulation. This transfer and reset is carried out in a manner that ensures that
coincident events are not lost.
The error count can also be polled by writing to the LASAR-155 Master
Reset / Load Meters register. Writing to the register loads all the error counter
registers in the SAR PMON, RSOP, RLOP, RPOP, RACP and TACP blocks.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 140