PM7375 Datasheet, PDF (325/430 Pages) PMC-Sierra, Inc – ATM SAR and PHY Processor for PCI Bus

DATA SHEET
PMC-931127
ISSUE 6
PM7375 LASAR-155
LOCAL ATM SAR & PHYSICAL LAYER
10.4.50 Register 0x3E0: PCID Host Read Mailbox Control
Bit
Bit 31
to
Bit 14
Bit 13
to
Bit 8
Bit 7
to
Bit 1
Bit 0
Type
R/W
R/W
Function
Unused
HRA[5:0]
Unused
MASTER
Default
XXXXH
00H
XXH
1
MASTER:
The MASTER bit is used to indicate the current master of the microprocessor to
PCI Host mailbox. When set to logic one, the microprocessor is the master,
When set to logic zero, the PCI Host is the master. Note, the PCI Host cannot
set this bit low. It can only force this bit high.
The MASTER bit will be set low by the microprocessor to indicate that the
PCI Host can access the mailbox for reads. The MASTER bit is set high by the
PCI Host to return control of the mailbox to the microprocessor.
If for some reason the microprocessor takes control of the
microprocessor to PCI Host mailbox when the PCI Host is the master, the PCI
Host is alerted using the MPTOP_ORI bit in the PCID Mailbox/Microprocessor
Interrupt Status/Enable register.
HRA[5:0]:
The HRA[5:0] bits specify the address of the microprocessor to PCI Host mailbox
location the PCI Host wishes to read from. HRA[5:0] is automatically post
incremented after every read of the PCID Host Read Mailbox Data register. If the
address reaches its limit, it wraps around to the start of the mailbox. The
HRA_ROI bit in the PCID Mailbox/Microprocessor Interrupt Status/Enable
register will be set high if this occurs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 309