PM7375 Datasheet, PDF (285/430 Pages) PMC-Sierra, Inc – ATM SAR and PHY Processor for PCI Bus

DATA SHEET
PMC-931127
ISSUE 6
PM7375 LASAR-155
LOCAL ATM SAR & PHYSICAL LAYER
10.4.12 Register 0x32C: PCID Rx Packet Descriptor Reference Large Buffer
Free Queue End
Bit
Bit 31
to
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type Function
Unused
R/W RPDRLFQE[15]
R/W RPDRLFQE[14]
R/W RPDRLFQE[13]
R/W RPDRLFQE[12]
R/W RPDRLFQE[11]
R/W RPDRLFQE[10]
R/W RPDRLFQE[9]
R/W RPDRLFQE[8]
R/W RPDRLFQE[7]
R/W RPDRLFQE[6]
R/W RPDRLFQE[5]
R/W RPDRLFQE[4]
R/W RPDRLFQE[3]
R/W RPDRLFQE[2]
R/W RPDRLFQE[1]
R/W RPDRLFQE[0]
Default
XXXXH
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RPDRLFQE[15:0]:
The RPDRLFQE[15:0] bits define bits 17 to 2 of the Receive Packet Descriptor
Reference Large Buffer Free Queue End address. This register is initialized by
the PCI Host. To calculate the physical end address of the RPDRLF queue, the
RPDRLFQE bits are added to the RQB field in the PCID Rx Queue Base
register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 269