TDA8029 Datasheet, PDF (8/58 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
Low power single card reader
Product specification
TDA8029
Additional features of the controller are:
• 80C51 central processing unit
• Full static operation
• Security bits: ROM 2 bits
• Encryption array of 64 bits
• 4-level priority structure
• 6 interrupt sources
• Full-duplex enhanced UART with framing error
detection and automatic address recognition
• Power control modes; clock can be stopped and
resumed, Idle mode and Power-down mode
• Wake-up from Power-down by falling edge on INT0_N,
INT1_N and RX with an embedded delay counter
• Programmable clock out
• Second DPTR register
• Asynchronous port reset
• Low EMI by inhibit ALE.
Table 1 gives a list of main features to get a better
understanding of the differences between a standard
80C51, an 8XC51FB and the embedded controller in the
TDA8029.
Table 2 shows an overview of the special function
registers.
Table 1 Principal blocks in 80C51, 8XC51FB and TDA8029
FEATURE
ROM
RAM
ERAM (MOVX)
PCA
WDT
T0
T1
T2
80C51
4 kbytes
128 bytes
no
no
no
yes
yes
no
4-level priority interrupt no
enhanced UART
no
delay counter
no
8XC51FB
16 kbytes
256 bytes
256 bytes
yes
yes
yes
yes
yes
lowest interrupt
priority-vector 002Bh
yes
yes
no
TDA8029
16 kbytes
256 bytes
512 bytes
no
no
yes
yes
yes
lowest interrupt
priority-vector 002Bh
yes
yes
yes
2003 Oct 30
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