TDA8029 Datasheet, PDF (23/58 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
Low power single card reader
Product specification
TDA8029
BIT
SYMBOL
DESCRIPTION⁽¹⁾
2
EX1
1
ET0
0
EX0
External interrupt 1 enable. EX1 = 1 enables the interrupt; EX1 = 0 disables the
interrupt.
Timer 0 interrupt enable. ET0 = 1 enables the interrupt; ET0 = 0 disables the interrupt.
External interrupt 0 enable. EX0 = 1 enables the interrupt; EX0 = 0 disables the
interrupt.
Notes
1. Details on interaction with the UART behaviour in Power-down mode are described in Section 8.15.
2. Do not write logic 1s to reserved bits. These bits may be used in future 80C51 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value
read from a reserved bit is indeterminate.
8.4.2 INTERRUPT PRIORITY (IP) REGISTER
Table 24 Interrupt priority register bits
BIT
7
Symbol
−
6
5
4
3
2
1
0
−
PT2
PS
PT1
PX1
PT0
PX0
Table 25 Description of register bits
BIT
7 and 6
5
4
3
2
1
0
SYMBOL
−
PT2
PS
PT1
PX1
PT0
PX0
DESCRIPTION
Not implemented. Reserved for future use; note 1.
Timer 2 interrupt priority. See Table 20.
Serial port interrupt priority. See Table 20.
Timer 1 interrupt priority. See Table 20.
External interrupt 1 priority. See Table 20.
Timer 0 interrupt priority. See Table 20.
External interrupt 0 priority. See Table 20.
Note
1. Do not write logic 1s to reserved bits. These bits may be used in future 80C51 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value
read from a reserved bit is indeterminate.
8.4.3 INTERRUPT PRIORITY HIGH (IPH) REGISTER
Table 26 Interrupt priority high register bits
BIT
7
Symbol
−
6
5
−
PT2H
4
PSH
3
PT1H
2
PX1H
1
PT0H
0
PX0H
Table 27 Description of register bits
BIT
7 and 6
5
4
3
SYMBOL
−
PT2H
PSH
PT1H
DESCRIPTION
Not implemented. Reserved for future use; note 1.
Timer 2 interrupt priority. See Table 20.
Serial port interrupt priority. See Table 20.
Timer 1 interrupt priority. See Table 20.
2003 Oct 30
23