TDA8029 Datasheet, PDF (12/58 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
Low power single card reader
Product specification
TDA8029
this mode. The Idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up
at the interrupt service routine and continued), or by a
hardware reset which starts the processor in the same
manner as a Power-on reset.
Power-down mode: To save even more power, a
Power-down mode can be invoked by software. In this
mode, the oscillator is stopped and the instruction that
invoked Power-down is the last instruction executed.
Either a hardware reset, external interrupt or reception
on RX can be used to exit from Power-down mode. Reset
redefines all the SFRs but does not change the on-chip
RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
With INT0_N, INT1_N or RX, the bits in register IE must be
enabled. Within the INT0_N interrupt service routine, the
controller has to read out the Hardware Status Register
(HSR @ 0Fh) and/or the UART Status register
(USR @ 0Eh) by means of MOVX-instructions in order to
know the exact interrupt reason and to reset the interrupt
source.
For enabling a wake up by INT1_N, the bit ENINT1 within
UCR2 must be set.
For enabling a wake up by RX, the bits ENINT1 and ENRX
within UCR2 must be set.
An integrated delay counter maintains internally INT0_N
and INT1_N LOW long enough to allow the oscillator to
restart properly, so a falling edge on pins RX, INT0_N and
INT1_N is enough for awaking the whole circuit.
Once the interrupt is serviced, the next instruction to be
executed after RETI will be the one following the
instruction that put the device into power-down.
Table 3 External pin status during Idle and Power-down mode
MODE
Idle
Power-down
PROGRAM MEMORY
internal
external
internal
external
ALE
1
1
0
0
PSEN_N PORT 0 PORT 1 PORT 2 PORT 3
1
data
data
data
data
1
float
data
address data
0
data
data
data
data
0
float
data
data
data
2003 Oct 30
12