TDA8029 Datasheet, PDF (22/58 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
Low power single card reader
Product specification
TDA8029
8.4 Interrupt priority structure
The TDA8029 has a 6-source 4-level interrupt structure.
There are three SFRs associated with the 4-level interrupt: IE, IP and IPH. The Interrupt Priority High (IPH) register
implements the 4-level interrupt structure. The IPH is located at SFR address B7h.
The function of the IPH is simple and when combined with the IP determines the priority of each interrupt. The priority of
each interrupt is determined as shown in Table 20.
Table 20 Priority bits
IPH BIT n
0
0
1
1
IP BIT n
0
1
0
1
INTERRUPT PRIORITY LEVEL
level 0 (lowest priority)
level 1
level 2
level 3 (highest priority)
Table 21 Interrupt table
SOURCE
POLLING PRIORITY
X0
1
T0
2
X1
3
T1
4
SP
5
T2
6
Notes
1. Level activated.
2. Transition activated.
REQUEST BITS
IE0
TF0
IE1
TF1
RI, TI
TF2, EXF2
HARDWARE CLEAR
N⁽¹⁾; Y⁽²⁾
Y
N⁽¹⁾; Y⁽²⁾
Y
N
N
VECTOR ADDRESS
(HEX)
03
0B
13
1B
23
2B
8.4.1 INTERRUPT ENABLE (IE) REGISTER
Table 22 Interrupt enable register bits
BIT
7
Symbol
EA
6
5
4
3
2
1
0
−
ET2
ES
ET1
EX1
ET0
EX0
Table 23 Description of register bits
BIT
SYMBOL
DESCRIPTION⁽¹⁾
7
EA
6
−
5
ET2
4
ES
3
ET1
Global disable. If EA = 0, all interrupts are disabled; If EA = 1, each interrupt can be
individually enabled or disabled by setting or clearing its enable bit.
Not implemented. Reserved for future use; note 2.
Timer 2 interrupt enable. ET2 = 1 enables the interrupt; ET2 = 0 disables the interrupt.
Serial port interrupt enable. ES = 1 enables the interrupt; ES = 0 disables the interrupt.
Timer 1 interrupt enable. ET1 = 1 enables the interrupt; ET1 = 0 disables the interrupt.
2003 Oct 30
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