TDA8029 Datasheet, PDF (24/58 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
Low power single card reader
Product specification
TDA8029
BIT
SYMBOL
DESCRIPTION
2
PX1H
1
PT0H
0
PX0H
External interrupt 1 priority. See Table 20.
Timer 0 interrupt priority. See Table 20.
External interrupt 0 priority. See Table 20.
Note
1. Do not write logic 1s to reserved bits. These bits may be used in future 80C51 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value
read from a reserved bit is indeterminate.
8.5 Dual Data Pointer (DPTR)
The dual DPTR structure is a way by which the TDA8029
will specify the address of an external data memory
location. There are two 16-bit DPTR registers that address
the external memory, and a single bit called DPS (bit 0 of
the AUXR1 register) that allows the program code to
switch between them.
The DPS bit should be saved by software when switching
between DPTR0 and DPTR1.
The GF bit (bit 2 in register AUXR1) is a general purpose
user-defined flag. Note that bit 2 is not writable and is
always read as a logic 0. This allows the DPS bit to be
quickly toggled simply by executing an INC AUXR1
instruction without affecting the GF or LPEP bits.
The instructions that refer to DPTR refer to the data pointer
that is currently selected using bit 0 of the AUXR1 register.
The six instructions that use the DPTR are listed in
Table 28 and an illustration is given in Fig.8.
Table 28 DPTR instructions
INSTRUCTION
COMMENT
INC DPTR
increments the data pointer by 1
MOV DPTR, #data 16 loads the DPTR with a 16-bit
constant
MOV A, @A + DPTR move code byte relative to
DPTR to ACC
MOVX A, @DPTR
move external RAM (16-bit
address) to ACC
MOVX @DPTR, A
move ACC to external RAM
(16-bit address)
JMP @A + DPTR
jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis
by specifying the low or high byte in an instruction which
accesses the SFRs.
handbook, full pagewidth
AUXR1.0
DPS
DPH
(83H)
DPTR1
DPTR0
DPL
(82H)
EXTERNAL
DATA
MEMORY
MHI007
2003 Oct 30
Fig.8 Dual DPTR.
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