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TDA8029 Datasheet, PDF (32/58 Pages) NXP Semiconductors – Low power single card reader | |||
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Philips Semiconductors
Low power single card reader
Product speciï¬cation
TDA8029
8.10.2.2 UART Receive Register (URR)
Table 46 UART receive register, address Dh, read
BIT
Symbol
Reset value
7
UR7
0
6
UR6
0
5
UR5
0
4
UR4
0
3
UR3
0
2
UR2
0
1
UR1
0
0
UR0
0
Table 47 Description of register bits
BIT
7 to 0
SYMBOL
UR[7:0]
DESCRIPTION
UART receive bits. When the microcontroller wants to read data from the card, it reads
it from this register in direct convention:
⢠With a synchronous card, only UR0 is relevant and is a copy of the state of the selected
card I/O
⢠When needed, this register may be tied to a FIFO whose length ânâ is programmable
between 1 and 8; if n > 1, then no interrupt is given until the FIFO is full and the
controller may empty the FIFO when required
⢠With a parity error:
â In protocol T = 0, the received byte is not stored in the FIFO and the error counter is
incremented. The error counter is programmable between 1 and 8. When the
programmed number is reached, then bit PE is set in the status register USR and
INT0_N falls LOW. The error counter must be reprogrammed to the desired value
after its count has been reached
â In protocol T = 1, the character is loaded in the FIFO and the bit PE is set to the
programmed value in the parity error counter.
⢠When the FIFO is full, then bit RBF in the status register USR is set. This bit is reset
when at least one character has been read from URR
⢠When the FIFO is empty, then bit FE is set in the status register USR as long as no
character has been received.
2003 Oct 30
32
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