74HC7403 Datasheet, PDF (4/28 Pages) NXP Semiconductors – 4-Bit x 64-word FIFO register; 3-state

Philips Semiconductors
4-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7403
SI
DIR
DATA INPUT 4
MR
OE
DOR _A
SO _A
SI _A 7403
DIR _A ^{FIFO A} QnA 4
DnA
MR
OE
SI _B
DOR _B
DIR _B
SOB
7403 ^Q nB 4
DnB ^{FIFO B}
MR
OE
MGA679
DOR
SO
DATA OUTPUT
Fig.4 Functional diagram.
FUNCTIONAL DESCRIPTION
A DIR flag indicates the input stage
status, either empty and ready to
receive data (DIR = HIGH) or full and
busy (DIR = LOW). When DIR and SI
are HIGH, data present at D₀ to D₃ is
shifted into the input stage; once
complete DIR goes LOW. When SI is
set LOW, data is automatically shifted
to the output stage or to the last
empty location. A FIFO which can
receive data is indicated by DIR set
HIGH.
A DOR flag indicates the output stage
status, either data available (DOR =
HIGH) or busy (DOR = LOW). When
SO and DOR are HIGH, data is
available at the outputs (Q₀ to Q₃).
When SO is set LOW new data may
be shifted into the output stage, once
complete DOR is set HIGH.
Expanded format (see Fig.17)
The DOR and DIR signals are used to
allow the “7403” to be cascaded. Both
parallel and serial expansion is
possible.
Serial expansion is only possible with
typical devices.
Parallel expansion
Parallel expansion is accomplished
by logically ANDing the DOR and DIR
signals to form a composite signal.
Serial expansion
Serial expansion is accomplished by:
• tying the data outputs of the first
device to the data inputs of the
second device
• connecting the DOR pin of the first
device to the SI pin of the second
device
• connecting the SO pin of the first
device to the DIR pin of the second
device.
September 1993
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