74HC7403 Datasheet, PDF (13/28 Pages) NXP Semiconductors – 4-Bit x 64-word FIFO register; 3-state

Philips Semiconductors
4-Bit x 64-word FIFO register; 3-state
With FIFO full; SI held HIGH in anticipation of empty location
Product specification
74HC/HCT7403
handbook, full pagewidth
SO INPUT
2 VM ⁽¹⁾
SI INPUT
1 VM ⁽¹⁾
DIR OUTPUT
t _PLH
bubble - up
delay
3
tW
VM ⁽¹⁾
5
4
MGA660
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.7 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.
Notes to Fig.7
1. FIFO is initially full, shift-in is held HIGH
2. SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins
3. DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input
4. DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again
5. SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.
September 1993
13