74HC7403 Datasheet, PDF (27/28 Pages) NXP Semiconductors – 4-Bit x 64-word FIFO register; 3-state

Philips Semiconductors
4-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7403
handbook, full pagewidth
sequence 1
sequence 2
sequence 3
sequence 4
sequence 5
sequence 6
SOB INPUT
DORB OUTPUT
(3) (4)
(8)
(14)
QnB OUTPUT
DIRB OUTPUT
DORA OUTPUT
(2)
(5)
(9)
(6)
(13)
(12)
QnA OUTPUT
DIRA OUTPUT
(10)
(7)
SIA INPUT
(1)
(11)
DnA INPUT
MR INPUT
MGA687
Fig.23 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.18).
Note to Fig.23
Sequence 1 (both FIFOS empty, starting SHIFT-IN process)
After a MR pulse has been applied FIFO_A and FIFO_B are empty. The DOR flags of FIFO_A and FIFO_B go LOW due to no
valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SO_B
is held HIGH and two SI_A pulses are applied (1). These pulses allow two data words to ripple through to the output stage
of FIFO_A and to the input stage of FIFO_B (2). When data arrives at the output of FIFO_B, a DOR_B pulse is generated (3).
When SO_B goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DOR_B goes
HIGH (4).
September 1993
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