74HC7403 Datasheet, PDF (26/28 Pages) NXP Semiconductors – 4-Bit x 64-word FIFO register; 3-state

Philips Semiconductors
4-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7403
handbook, full pagewidth
DOR _B
VM ⁽¹⁾
SO _B
VM ⁽¹⁾
DIR _B SO _A
2
bubble - up
delay
3
VM ⁽¹⁾
DORA SI _B 1
Q _nA DnB
DIR _A
4 VM ⁽¹⁾
5
bubble - up
delay
6
VM ⁽¹⁾
MGA667
Fig.22 FIFO to FIFO communication; output timing under full condition.
Notes to Fig.22
1. FIFO_A and FIFO_B initially full, SI_B held HIGH in anticipation of shifting in new data as an empty location bubbles-up
2. Unload one word from FIFO_B; SO pulse applied, results in DOR pulse
3. DIR_B and SO_A pulse HIGH; (bubble-up delay after SO_B LOW) data is loaded into FIFO_B as a result of the DIR pulse,
data is shifted out of FIFO_A
4. DOR_A and SI_B go LOW; flag indicates the output stage of FIFO_A is busy, shift-in to FIFO_B is complete
5. DOR_A and SI_B go HIGH; flag indicates valid data is again available at FIFO_A output stage, SI_B is held HIGH, awaiting
bubble-up of empty location
6. DIR_A goes HIGH; (bubble-up delay after SO_A LOW) an empty location is present at input stage of FIFO_A.
September 1993
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