74HC7403 Datasheet, PDF (16/28 Pages) NXP Semiconductors – 4-Bit x 64-word FIFO register; 3-state

Philips Semiconductors
4-Bit x 64-word FIFO register; 3-state
With FIFO empty; SO is held HIGH in anticipation
Product specification
74HC/HCT7403
handbook, full pagewidth
SI INPUT
2 VM ⁽¹⁾
SO INPUT
1 VM ⁽¹⁾
DOR OUTPUT
Qn OUTPUT
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
t _PLH
tW
ripple through
delay
3 VM ⁽¹⁾
6
5
t _PHL t _PLH
4
MGA658
Fig.10 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation
delay from the DOR pulse to the Q_n output.
Notes to Fig.10
1. FIFO is initially empty, SO is held HIGH
2. SI pulse; loads data into FIFO and initiates ripple through process
3. DOR flag signals the arrival of valid data at the output stage
4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the
DOR pulse to the Q_n output
5. DOR goes LOW; data shift-out is complete, FIFO is empty again
6. SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty.
September 1993
16