74HC7403 Datasheet, PDF (15/28 Pages) NXP Semiconductors – 4-Bit x 64-word FIFO register; 3-state

Philips Semiconductors
4-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7403
handbook, full pagewidth
1st SO pulse
1/f _max
2nd SO pulse
SO INPUT
2
VM ⁽¹⁾
VM ⁽¹⁾
4
6
DOR OUTPUT
t _PHL
1
t_W
t _PLH
3
5
VM ⁽¹⁾
64th SO pulse
7
Qn OUTPUT
1st word
2nd word
64th word
MGA661
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.9 Waveforms showing the SO input to DOR output propagation delay. The SO pulse widths and maximum
pulse frequency.
Notes to Fig.9
1. DOR HIGH; no data transfer in progress, valid data is present at output stage
2. SO set HIGH; results in DOR going LOW
3. DOR goes LOW; output stage “busy”
4. SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location “bubbles-up” to input
stage
5. DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay
6. Repeat process to unload the 3rd through to the 64th word from FIFO
7. DOR remains LOW; FIFO is empty.
September 1993
15