74HC7403 Datasheet, PDF (24/28 Pages) NXP Semiconductors – 4-Bit x 64-word FIFO register; 3-state

Philips Semiconductors
4-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7403
Expanded format
Figure 20 shows two cascaded FIFOs
providing a capacity of 128 words x
4 bits. Figure 21 shows the signals on
the nodes of both FIFOs after the
application of a SI pulse, when both
FIFOs are initially empty. After a
ripple through delay, data arrives at
the output of FIFO_A. Due to SO_A
being HIGH, a DOR_A pulse is
generated. The requirements of SI_B
and D_nB are satisfied by the DOR_A
pulse width and the timing between
the rising edge of DOR_A and Q_nA.
After a second ripple through delay,
data arrives at the output of FIFO_B.
Figure 22 shows the signals on the
nodes of both FIFOs after the
application of a SO_B pulse, when both
FIFOs are initially full. After a
bubble-up delay a DIR_B pulse is
generated, which acts as a SO_A pulse
for FIFO_A. One word is transferred
from the output of FIFO_A to the input
of FIFO_B. The requirements of the
SO_A pulse for FIFO_A is satisfied by
the pulse width of DOR_B. After a
second bubble-up delay an empty
space arrives at D_nA, at which time
DIR_A goes HIGH. Figure 23 shows
the waveforms at all external nodes of
both FIFOs during a complete shift-in
and shift-out sequence.
SI
DIR
DATA INPUT 4
MR
OE
DOR _A
SO _A
SI _A 7403
DIR _A ^{FIFO A} QnA 4
DnA
MR
OE
SI _B
DOR _B
DIR _B
SOB
7403 ^Q nB 4
DnB ^{FIFO B}
MR
OE
MGA679
DOR
SO
DATA OUTPUT
Fig.20 Cascading for increased word capacity; 128 words x 4 bits.
Note to Fig.20
The “7403” is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figures 21 and 22 demonstrate the intercommunication timing between
FIFO_A and FIFO_B. Figure 23 provides an overview of pulses and timing of two cascaded FIFOs, when shifted full and
shifted empty again.
September 1993
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