74HC7403 Datasheet, PDF (25/28 Pages) NXP Semiconductors – 4-Bit x 64-word FIFO register; 3-state

Philips Semiconductors
4-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7403
handbook, full pagewidth
DIR _A
VM ⁽¹⁾
SI _A
VM ⁽¹⁾
DORA SI _B
2
ripple through
delay
4
VM ⁽¹⁾
DIR _B SO _A 1
Q _nA DnB
DOR _B
Q _nB
5 VM ⁽¹⁾
6
3
ripple through
delay
7 _VM ⁽¹⁾
MGA666
Fig.21 FIFO to FIFO communication; input timing under empty condition.
Notes to Fig.21
1. FIFO_A and FIFO_B initially empty, SO_A held HIGH in anticipation of data
2. Load one word into FIFO_A; SI pulse applied, results in DIR pulse
3. Data-out _A/data-in _B transition; valid data arrives at FIFO_A output stage after a specified delay of the DOR flag,
meeting data input set-up requirements of FIFO_B
4. DOR_A and SI_B pulse HIGH; (ripple through delay after SI_A LOW) data is unloaded from FIFO_A as a result of the data
output ready pulse, data is shifted into FIFO_B
5. DIR_B and SO_A go LOW; flag indicates input stage of FIFO_B is busy, shift-out of FIFO_A is complete
6. DIR_B and SO_A go HIGH automatically; the input stage of FIFO_B is again able to receive data, SO is held HIGH in
anticipation of additional data
7. DOR_B goes HIGH; (ripple through delay after SI_B LOW) valid data is present one propagation delay later at the FIFO_B
output stage.
September 1993
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