74HC7403 Datasheet, PDF (14/28 Pages) NXP Semiconductors – 4-Bit x 64-word FIFO register; 3-state

Philips Semiconductors
4-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7403
Master reset applied with FIFO full
handbook, halfpage
MR INPUT
2
DIR OUTPUT
1
DOR OUTPUT
VM ⁽¹⁾
t_W
t _PLH
VM ⁽¹⁾
3
t _PHL
4
VM ⁽¹⁾
t _PHL
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Qn OUTPUT
5
MGA668
Fig.8 Waveforms showing the MR input to DIR, DOR and Q_n output propagation delays and the MR pulse width.
Notes to Fig.8
1. DIR LOW, output ready HIGH; assume FIFO is full
2. MR pulse LOW; clears FIFO
3. DIR goes HIGH; flag indicates input prepared for valid data
4. DOR goes LOW; flag indicates FIFO empty
5. Q_n outputs go LOW (only last bit will be reset).
September 1993
14