74HC7403 Datasheet, PDF (12/28 Pages) NXP Semiconductors – 4-Bit x 64-word FIFO register; 3-state

Philips Semiconductors
4-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7403
AC WAVEFORMS
Shifting in sequence FIFO empty to FIFO full
handbook, full pagewidth
1st word
1/f max
2nd word
SI INPUT
2
VM ⁽¹⁾
VM ⁽¹⁾
4
6
DIR OUTPUT
t _PHL
1
t_W
t _PLH
5
3
64th word
7
Dn INPUT
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
MGA659
Fig.6 Waveforms showing the SI input to DIR output propagation delay, the SI pulse width and SI maximum
pulse frequency.
Notes to Fig.6
1. DIR initially HIGH; FIFO is prepared for valid data
2. SI set HIGH; data loaded into input stage
3. DIR goes LOW, input stage “busy”
4. SI set LOW; data from first location “ripple through”
5. DIR goes HIGH, status flag indicates FIFO prepared for additional data
6. Repeat process to load 2nd word through to 64th word into FIFO
DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.
September 1993
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