PI2EQX5804CNJE Datasheet, PDF (9/23 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis

PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
I²C Operation
The integrated I²C interface operates as a slave device, supporting standard rate operation of 100Kbps, with
7-bit addressing mode. The data byte format is 8 bit bytes. The bytes must be accessed in sequential order
from the lowest to the highest byte with the ability to stop after any complete byte has been transferred. Ad-
dress bits A4, A1 and A0 are programmable to support multiple chips environment. The data is loaded until a
Stop sequence is issued.
Configuration Register Summary
Byte Mnemonic Function
0 SIG
Signal Detect, indicates valid input signal level
1 RX50
Receiver Detect Output, indicates whether a receiver load was detected
2 LBEC
Loopback and Emphasis Control, provides for control of the loopback function and emphasis mode (pre-
emphasis or de-emphasis)
3 INDIS
Channel Input Disable, controls whether s channels input buffer is enabled or disabled
4
OUTDIS
Channel Output Disable: Controls whether a channels output buffer is enabled or disabled
5 RESET
Channel Reset
6 PWR
Power Down Control, enables power down for each channel individually
7 RXDE
Receiver Detect Enable, controls the receiver detect operation
8 AEOC
A-Channels Equalizer and Output Control
9 AEOC
B-Channels Equalizer and Output Control
10 RSVD
Reserved
11 RSVD
Reserved
3.3V to 1.2V Bi-directional Level Shifter
If the I²C controller is 3.3V bus, the bi-directional level shifter is used to interconnect two sections of an I²C-
bus system, each section with a different supply voltage and different logic levels. In the bus system of Figure
2 the left section has pull-up resistors and devices connected to a 1.2 Volt supply voltage, the right section has
pull-up resistors and devices connected to a 3.3 Volt supply voltage. The devices of each section have I/O’s
with supply voltage related logic input levels and an open drain output configuration.
The level shifter for each bus line is identical and consists of one discrete N-channel enhancement MOS-FET,
T1 for the serial data line SDA and T2 for the serial clock line SCL. The gates (g) has to be connected to the
lowest supply voltage VDD1 (1.2V), the sources (s) to the bus lines of the “Lower voltage” section, and the
drains (d) to the bus lines of the “Higher voltage” section. The diode between the drain (d) and substrate is
inside the MOS-FET present as n-p junction of drain and substrate.
09-0001
9
PS8926B
06/08/09