PI2EQX5804CNJE Datasheet, PDF (4/23 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis

PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Pin #
F10, F9, F7
E9
F2
Power Pins
Pin Name Type
SEL[0:2]_B I
SIG_A
O
SIG_B
O
Description
Selection pins for Channel Bx Equalization (see Equalizer Configuration Table)
w/ 100K-Ohm internal pull up
Signal detect output pin for Channel A0. SIG_A=High represents a input signal >
threshold at the differential inputs.
Signal detect output pin for Channel B0. SIG_B=High represents a input signal >
threshold at the differential inputs.
B2, B3, B8, B9, C2,
C3, C8, C9, H2,
H3, H8, H9, J2, J3,
GND
J8, J9
PWR Supply Ground
A1, A4, A7, A10,
B6, D1, D4, D7,
D10, G1, G4, G7, V_DD
G10, K1, K4, K7,
K10
PWR 1.2V Supply Voltage
DESCRIPTION of OPERATION
Configuration Modes
Device configuration can be performed in two ways depending on the state of the MODE input. MODE de-
termines whether IC configuration status is from the input pins or via I²C control. When MODE is set high,
the configuration input pins set the configuration operating state as stored in configuration registers. While
MODE is set high, changes to these control registers are disabled and the initial condition is protected from
any changes to insuring a known operating state. When the MODE pin is low, reprogramming of these control
registers via I²C is allowed. Note that the MODE pin is not latched, and is always active to enable or disable
I²C access.
During initial power-on, the value at the configuration input pins: LB#, RESET#, PD#, RXD_A and RXD_B,
DE_A, DE_B, SEL0_A, SEL1_A, SEL2_A, D0_A, D1_A, D2_A, S0_A, S1_A, SEL0_B, SEL1_B, SEL2_B,
D0_B, D1_B, D2_B, S0_B, S1_B, will be latched to the configuration registers as initial startup states.
09-0001
4
PS8926B
06/08/09